The present invention relates to a nonvolatile semiconductor memory capable of changing memory cell data in units of bytes.
EEPROMs are conventionally known as nonvolatile semiconductor memories for changing memory cell data in units of bytes.
Reference 1 (W. Johnson et al., “A 16 Kb Electrically Erasable Nonvolatile Memory,” ISSCC Digest of Technical Papers, PP. 152–153, February 1982) has proposed an EEPROM which changes memory cell data in units of bytes using FLOTOX (Floating Gate Tunnel Oxide) cells.
FIG. 65 is a plan view showing an example of a memory cell section of an EEPROM capable of byte erase. FIG. 66 is a sectional view taken along a line LXVI—LXVI in FIG. 65.
This EEPROM uses FLOTOX cells in the memory cell section. As a characteristic feature of a FLOTOX cell, an about 10-nm tunnel oxide film 22a is formed between an N+ drain 20a and a floating gate 21a, and charges are transferred between the N+ drain 20a and the floating gate 21a by applying an electric field to the tunnel oxide film 22a. 
A current flowing to the tunnel oxide film 22a is an F-N (Fowler-Nordheim) tunneling current generated by the F-N tunneling phenomenon.
FIG. 67 is a view showing the energy band of a MOS capacitor section.
When an electric field is applied to the MOS capacitor (N+ drain-tunnel oxide film-floating gate), an F-N tunneling current flows to the tunnel oxide film (SiO2) on the basis of equation (1):
                              I          =                                    S              ·              α              ·                              E                2                                      ⁢                                                  ⁢                          exp              ⁡                              (                                                      -                    β                                    /                  E                                )                                                    ⁢                                  ⁢                                  ⁢                              S            ⁢                          :                        ⁢                                                  ⁢            area                    ,                      E            ⁢                          :                        ⁢                                                  ⁢            electric            ⁢                                                  ⁢            field                          ⁢                                  ⁢                  α          =                                                                      q                  3                                /                8                            ⁢                                                          ⁢              π              ⁢                                                          ⁢              h              ⁢                                                          ⁢                              Φ                B                                      =                          6.94              ×                                                10                                      -                    7                                                  ⁢                                                                  [                                  A                  ⁢                                      /                                    ⁢                                      V                    2                                                  ]                                                    ⁢                                  ⁢                                                            β                =                                                      -                    4                                    ⁢                                                            (                                              2                        ⁢                        m                                            )                                        0.5                                    ⁢                                      Φ                    B                                    ⁢                                      1.5                    /                    3                                    ⁢                                                                          ⁢                  hq                                                                                                        =                                  2.54                  ×                                                            10                      8                                        ⁢                                                                                  [                                          V                      ⁢                                              /                                            ⁢                      cm                                        ]                                                                                                          (        1        )            
As is apparent from equation (1), the electric field with which the F-N tunneling current starts flowing is about 10 MV/cm. This electric field theoretically corresponds to a case wherein a voltage of 10V is applied to a tunnel oxide film of 10 nm.
Referring to FIGS. 65 and 66, assume that when a voltage is applied between the N+ drain 20a and a control gate 23a, the capacitance ratio (coupling ratio) between the control gate 23a and the floating gate 21a is 0.5.
In this case, to apply a voltage of 10V to the tunnel oxide film 22a between the N+ drain 20a and the floating gate 21a, a voltage as high as 20V must be applied between the N+ drain 20a and the control gate 23a. 
For example, in the erase mode, the N+ drain 20a is set at 0V and the control gate 23a at 20V to move electrons from the N+ drain 20a to the floating gate 21a. In the “1” program mode, the N+ drain 20a is set at 20V and the control gate 23a at 0V to move electrons from the floating gate 21a to the N+ drain 20a. 
The disadvantage of the EEPROM using FLOTOX cells is that two elements, a memory cell and a select transistor, are required to store 1-bit data, as shown in FIGS. 65 and 66.
FIG. 68 shows another example of the memory cell section of the EEPROM capable of byte erase.
As characteristic features of this EEPROM, FLOTOX cells are used in the memory cell section, and a byte control transistor Tr is prepared in correspondence with memory cells of 8 bits (1 byte).
Table 1 shows bias conditions in each mode of this EEPROM.
TABLE 1Unselected ByteUnselected ByteConnected to theConnected toSame Word Linethe Same BitSelectedas That ofLine as That ofModeByteSelected ByteSelected ByteEraseWordHighHighLow(“0”LineHighLowHighprogramming)ByteControlBit LineLowLowLow“1”WordHighHighLowProgrammingLineLowLowLowByteControlBit LineHigh orLowHigh or Low*2Low*1*1= Data Dependent*2= Don't Care
When such a memory cell section is used, various operation errors (disturbances) can be avoided. However, since 2+(⅛) transistors are required to store 1-bit data, the cell area increases to result in an increase in cost.
Flash EEPROMs aim at eliminating this problem. A conventional EEPROM is very convenient because data can be erased or programmed in units of 1-bit data.
However, when a computer hard disk requiring a large memory capacity is to be formed from an EEPROM, the EEPROM need not have a function of erasing or programming data in units of 1-bit data. In most hard disks, data is often erased or programmed in units of sectors (or in units of blocks).
It is more advantageous to attain a large memory capacity by cell area reduction and reduce the cost of products while omitting the function of changing data in units of 1-bit data. On the basis of such an idea, flash EEPROMs have been developed.
Details of a flash EEPROM are described in, e.g., reference 2 (F. Masuoka et al., “A new Flash EEPROM cell using triple polysilicon technology,” IEDM Technical Digest, pp. 464–467 December 1984).
FIG. 69 shows the structure of a memory cell of a flash EEPROM.
The memory cell of the flash EEPROM has a control gate and floating gate, like a memory cell of a UV erase EPROM. In the flash EEPROM, data is programmed by injecting hot electrons to the floating gate, as in the UV erase EPROM. Data is erased by removing electrons from the floating gate using the F-N tunneling phenomenon, like a byte EEPROM.
In the flash EEPROM, the erase operation for the individual memory cells is the same as in the byte EEPROM. However, the operation for the entire memory cell array is completely different from that in the byte EEPROM. More specifically, the byte EEPROM erases data in units of bytes while the flash EEPROM erases all bit data at once. Employing such an operation method, the flash EEPROM realizes a memory cell section with one transistor per bit and achieves a large memory capacity.
In the flash EEPROM, data can be programmed in units of bits, like the UV erase EPROM. More specifically, the flash EEPROM is the same as the UV erase EPROM in that all bit data are erased at once, and data can be programmed in units of bits.
To realize a memory chip with a large memory capacity, a NAND flash EEPROM has been proposed on the basis of the above-described flash EEPROM.
Reference 3 (F. Masuoka et al., “New ultra high density EPROM and Flash EEPROM with NAND structured cell,” IEDM Technical Digest, pp. 552–555 December 1987) discloses a NAND flash EEPROM.
The memory cell array portion of a NAND EEPROM has a NAND unit in which a plurality of (e.g., 16) memory cells are serially connected to form a NAND series with select transistors connected to its two ends, respectively, as shown in FIGS. 70 and 71.
In the NAND EEPROM, a bit line contact section and source line need be formed not for each memory cell but for one NAND unit. Two adjacent memory cells of the plurality of memory cells forming the NAND series share one diffusion layer. For this reason, the memory cell size per bit can be largely reduced, and a memory chip having a large memory capacity can be realized.
FIG. 72 shows a NOR flash EEPROM. In the NOR flash EEPROM, a 1-bit (one) memory cell is formed between a bit line and a source line.
In terms of cost, the above-described NAND flash EEPROM has a characteristic feature suitable to a large-capacity file memory: the cost per bit is low because the cell size can be reduced as compared to the NOR flash EEPROM. In terms of function, the NAND flash EEPROM has a higher data change rate and lower power consumption than those of the NOR flash EEPROM.
In terms of function, the NAND flash EEPROM is characterized in the scheme for changing data. More specifically, the NAND flash EEPROM achieves program and erase by charge transfer between the silicon substrate (channel) and the floating gate.
To transfer charges, the F-N tunneling phenomenon is used. A current necessary for programming is an F-N tunneling current flowing from the silicon substrate (channel) to the floating gate. Unlike the NOR flash EEPROM that uses hot electrons for programming, the NAND flash EEPROM has very small current consumption.
In a 64-Mbit NAND flash EEPROM, data of one page (512 bytes) can be programmed in 200 μs. This programming time is shorter than that for one block in the NOR flash EEPROM.
Table 2 shows comparison between the characteristic features of the NAND flash EEPROM and those of the NOR flash EEPROM.
TABLE 2NANDNORAdvantage{circle around (1)} Programming rate is{circle around (1)} Random access rate ishighhigh{circle around (2)} Erase rate is high{circle around (2)} Data can be{circle around (3)} Block size is smallprogrammed in units ofand file management isbytes at randomeasyDisadvantage{circle around (1)} Random access rate is{circle around (1)} Random access rate islowlow{circle around (2)} Data cannot be{circle around (2)} Erase rate is lowprogrammed in units ofbytesApplicationReplacement for hard diskReplacement forPurposeand floppy disk, and dataconventional EPROM, andrecorder for portablecontrol memory forterminal (handy terminal,control device, BIOS ofvoice recording,PC, portable telephone,electronic still camera)and HDDand Fax/modem
As shown in Table 2, the advantages and disadvantages of these memories are complementary to each other.
For the application purpose, the NAND flash EEPROM is used aiming at changing data in units of blocks. For example, in a digital camera having 300,000 pixels requires a memory capacity of about 0.5 Mbit for a photograph of one shot. When one block of the NAND flash EEPROM has a memory capacity of about 0.5 Mbit or more, photograph data of one shot can be stored in one block. In this case, data is erased in units of blocks. More specifically, photograph data of one shot is erased by erasing data of memory cells in one block.
On the other hand, the NOR flash EEPROM is capable of random access at a high speed of 100 ns and is widely used as a control program memory for, e.g., a portable telephone.
As described above, nonvolatile semiconductor memories have been developed as EEPROM (conventional type)→flash EEPROM→NAND flash EEPROM. The memory size, i.e., the cost per bit (bit cost) is reduced by sacrificing the function of changing data in units of bytes.
However, for, e.g., a nonvolatile memory embedded LSI which has received a great deal of attention recently, the function of changing data in units of bytes is required. For example, when an IC card used in a system for managing income and expenditure uses a flash EEPROM as an internal memory, data must be erased in units of blocks even when the data need a partial change. For this reason, the function of changing data in units of bytes is essential for such a system.
To cope with this situation, a byte EEPROM capable of changing data in units of bytes is required. However, the byte EEPROM has the large number of elements per bit, as described above, and therefore, is disadvantageous in increasing the memory capacity or reducing the bit cost.
Nonvolatile semiconductor memories of the current mainstream are flash EEPROMs (e.g., NOR type and NAND type). Hence, development of a byte EEPROM having the same process and scheme for changing data as those of a flash EEPROM makes it possible to produce EEPROMs meeting the requirements of the market at low cost.